Synthesizing Unit counter. Related source file is counters_1. 4-bit Unsigned Up/Down counter with. Following is the VHDL code for a 4-bit unsi gned up/down. VHDL code for counters with testbench, VHDL code for up counter. Several 4-bit counters including up counter, down counter and up-down counter are implemented in. You can't synthesize something that uses both clock edges under the IEEE-1076.6 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis. It's not a recognized clocking method. Making a modulo 10 counter. Nice with some HDL on Code Review. I'll contribute with my opinions. All-in-all, I find the code all well-written. Opinions not already covered in previous answers • A more standard way of setting count at reset would be (others => '0'). • That is, as opposed to hard-coding a bit/hex literal - even if you for some reason hard-code the width as you have done, (others => '0') is more standard in this case. • You might have a good reason for asynchronous reset, but if not, synchronous reset is a better habit. • You often see these asynchronous resets, it is unfortunately a more common habit, since that's what is (or was) most often taught. • See my motivations here: Opinions already covered/partly covered Somewhat in order of importance (in my subjective opinion). • Define the roll-over behaviour. • The behaviour is actually defined for an unsigned in numeric_std: any carry bits will be ignored so the unsigned will roll-over. However, neither simulators nor synthesis tools should be trusted on following this. (And even less, humans reading the code.) Also; it is good to really think about what behaviour you desire, or is the most stable: roll-over or saturate? I'll take the chance to give two comments on this choice: • For synthesis, roll-over rather than saturation will yield less logic and improved timing. The tool will be able to use a counter macro right-off. • If reaching max count is expected never to happen, add an assertion so a simulation will flag in that case. Then still code the RTL behaviour explicitly to roll-over (less logic, better timing) if there aren't stability reasons to code it to saturate. ![]() • Parameterize the width. Put it in a constant or generic. • Generate the clock separately (e.g. Contrary to what Aseem Bansal states, there is no need to use std_logic alone. Your use of std_ulogic is fine. One place where there is a trade-off to be pondered is on your top-level entity (the one which defines the whole chip). The tools that generate the output will create you a simulation model with all the gates and delays in, but it will have std_logic on the IO pins. This can be plugged straight into your existing testbench if you've already used std_logic at the top. You can avoid lots of duplicated typing by using direct instantiation. You don't need this at all: component counter32 port ( clk: in std_ulogic; ena: in std_ulogic; rst: in std_ulogic; q: out std_ulogic_vector(31 downto 0)); end component; if you do this: dut: entity work.counter32 port map ( clk => clk, ena => ena, rst => rst, q => q); This is the preferred method these days. In your testbench, I would separate out the clock generation to its own process. Or even to a single line: clk. Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcdupcounter1 is Port ( clk,rst: in STD_LOGIC; q: inout STD_LOGIC_VECTOR (3 downto 0)); end bcdupcounter1; architecture Behavioral of bcdupcounter1 is signal div:std_logic_vector(22 downto 0); signal clkd:std_logic; begin process(clkd) begin if rising_edge(clk)then div. Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcddowncounter is Port ( clk,rst: in STD_LOGIC; q: inout STD_LOGIC_VECTOR (3 downto 0)); end bcddowncounter; architecture Behavioral of bcddowncounter is signal div:std_logic_vector(22 downto 0); signal clkd:std_logic; begin process(clkd) begin if rising_edge(clk)then div.
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